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Lattice Semiconductor
CSIX Level 1 IP Core User’s Guide
ready signal. The deassertion of the local ready signal should signal the user application to pause outbound data-
?ows, thereby preventing the outbound FIFOs from over?owing.
The inbound Generic FIFO Bridge interface employs two Generic FIFO Bridge buses so that user applications can
process the control and data streams independently. The inbound Generic FIFO Bridge bus implements the follow-
ing signals: 36-bit databus, data available, read enable, empty ?ag, and clock. The data available signal asserts
when the associated FIFO’s low watermark is exceeded. When the read enable is asserted, data?ow begins one
clock later. When the read enable is deasserted, data?ow halts one clock later. The empty ?ag asserts when the
FIFO occupancy is zero. The clock signal can be any frequency up to 100MHz. However, keep in mind that the
CSIX interface operates at 100MHz. Therefore, if the Generic FIFO Bridge interface operates more slowly than
proper system FIFO depth, watermark settings, and ?ow control mechanisms must all function appropriately to pre-
vent the core’s FIFOs from over?owing.
Outbound Path
The outbound path monitors the internal FIFOs and passes all available Cframes to the external CSIX interface.
User applications must load valid Cframes into the outbound FIFOs via the two outbound Generic FIFO Bridge
interfaces. Major functions of the outbound path include: obeying the CSIX link startup process, continuously
checking frame availability from control and data FIFOs in round robin fashion, unloading internal FIFOs and driv-
ing the external CSIX interface, and facilitating link-level ?ow control and backpressure.
As stated in the Network Processor Forum’s CSIX-L1 Speci?cation, version 1.0, dated 8/5/2000, the outbound
CSIX interface must follow a prescribed startup process. Three states are de?ned, “reset”, “transmit_idle”, and “nor-
mal”. After exiting a reset state, the outbound CSIX interface must enter the “transmit_idle” state and begin trans-
mitting idle frames with ready bits deasserted. If the inbound interface detects idle frames (ready bit states
irrelevant) then the outbound path must send idle frames with the ready bits asserted. The outbound interface
assumes a “normal” state only after the inbound path receives valid idle frames with the ready bits asserted high.
The core’s startup FSM follows a modi?ed form of this process. While in the “transmit_idle” state, the core will only
send idle frames with ready bits asserted after both receiving idle frames on the inbound CSIX interface and receiv-
ing asserted remote control/data signals from the outbound Generic FIFO Bridge interface.
The outbound Generic FIFO Bridge interface is similar to the inbound path except that the direction of data?ow is
reversed. The following signals are implemented: 36-bit databus, write enable, full ?ag, and clock. FIFO data writes
occur coincident with write enable assertion. The EOF ?ag should be asserted during the penultimate word as
shown in Figure 8. The full ?ag is asserted when the FIFO occupancy is almost full (as de?ned by the high water-
mark for the FIFO). The clock can be any frequency up to 100MHz. However, at lower frequencies, the average
CSIX throughput rate is limited by the Generic FIFO Bridge clock rate.
The outbound FIFOs are similar to those used in the inbound path. An outbound transmit controller reads outbound
FIFOs and determines which type of frame appears on the external CSIX interface.
There are four ?ow control mechanisms associated with the outbound path. The ?rst mechanism responds to con-
trol or data ready-bit deassertions from the inbound CSIX interface. If either of these bits is deasserted, the corre-
sponding outbound FIFO is prohibited from further reads after the current Cframe ends. This effects a CSIX
“pause” and remains active as long as the inbound ready bit is deasserted.
The second ?ow control mechanism is associated with the remote data/control ready signals that enter the out-
bound path along with the Generic FIFO Bridge interfaces. These signals indicate the CSIX link ready statuses
from remotely connected CSIX entities. For example, a traf?c manager and a fabric device interconnected by two
back-to-back CSIX IP cores. The remote ready signals connect directly to the outgoing ready bits of the CSIX inter-
face. A deasserted remote ready signal causes the external CSIX network element to pause transmission on the
inbound data path, thereby easing the congestion being experienced by the remote device.
The third ?ow control mechanism is associated with the inbound FIFOs. If either of the inbound “nearly-full” signals
are asserted, the outgoing ready bits of the CSIX interface are deasserted. This in-turn causes the external CSIX
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相关PDF资料
CSIX-PI40-O4-N1
INTERFACE IP CSIX TO PI40 ORCA 4
CT0805S14BAUTOG
VARISTOR 14VRMS 0805 SMD AUTO
CT1206K17G
VARISTOR 17VRMS 1206 SMD
CTB-B-B-15
CIRCUIT BREAKER ROCKER 15A SP BK
CU3225K17AUTOG2
VARISTOR AUTO 17VRMS 3225 SMD
CU3225K250G2K1
VARISTOR STD 250VRMS 3225 SMD
CV10-RP-M-0
CONN JACK STR COAXIAL SMD
CVM50XM
MEMBER MOD PIC12C508/PIC12C509
相关代理商/技术参数
CSIX-PI40-O4-N1
功能描述:输入/输出控制器接口集成电路 CSIX to PI40 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray
CSJ-100
制造商:GREENLEE TOOL CO 功能描述:Digital Open Jaw Clampmeter 制造商:Greenlee Textron Inc 功能描述:CLAMPMETER
CSJ-23
功能描述:EXTRACTION TOOL FOR SCS RoHS:否 类别:工具 >> 插入，抽取 系列:* 标准包装:1 系列:* 其它名称:0011-03-00080011-03-0008-E00110300080011030008-E11-03-0008-E1103000811030008-EQ4729393AT0980176A
CSJ32C1
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C3
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C5
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E1
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E3
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals